CDS Example Timing Pattern
|LSYNC should occur sometime before the first
pixel clock edge.
LINE cause vertical register to increment at both edges; odd rows on positive edge and even rows on negative edge.
RESETB clock is an active low asynchronous reset which resets the entire currently selected row.
READ is an active high clock. When active, pixel outputs are allowed to pass to the column bus for subsequent off chip.
Clock must be low when fsync is pulsed low.
Note: Pixel Clock must be low when lsync is pulsed low.
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